SpiderCSS: Scalable Fault-Tolerant CSS State Preparation
Abstract
Fault-tolerant preparation of logical states is a critical primitive for the realization of large-scale fault-tolerant quantum computing. SpiderCSS introduces a scalable compilation pipeline that generates highly optimized, fault-tolerant state preparation circuits for arbitrary Calderbank–Shor–Steane (CSS) codes. Starting from an idealized bipartite ZX-diagram specification of a CSS state, we apply fault-equivalent rewrites and precomputed well-ordered Cat states to construct a diagram that is CNOT-minimal both within each component and across their interconnections—provably preserving fault tolerance by construction without expensive verification.
From CSS Stabilizers to Fault-Tolerant Quantum Circuits
Choose how you want to interact with SpiderCSS: explore the step-by-step theoretical walkthrough or synthesize circuits directly with the full compiler.
CSS Code & Target Logical State Specification
Select from 43 benchmarked CSS codes or define custom parity-check matrices / Pauli strings, target basis, and distance .
0/1Bipartite ZX-Diagram & Column-Permuted RREF Basis Optimization
Different stabilizer generator bases yield different bipartite ZX-diagrams. Column-permuted Gaussian elimination over embeds an identity submatrix into the pivot columns (guaranteeing the unique-ones property) while minimizing Eq. (8) CNOT cost.
Eq. (8) Fault-Tolerant CNOT & Flag Cost Model
is_perfect): Col (X) spiders unfuse at instead of Actual Circuit: 15 CNOTs, 3 FlagsBipartite ZX-State Diagram (RREF Form)
3 row spiders () • 4 non-pivot spiders () • all 7 output legs on the right • 9 idealized internal edges
How would you like to proceed from the idealized bipartite ZX-diagram?
Explore the theoretical fault-equivalent ZX-calculus rewrites (Section III.A) or jump directly into the Algorithm 1 compiler pipeline (Section IV).
Global Port Matching (G_global, D_global) Without Backtracking
Each external bipartite edge is matched to the earliest unassigned 3-ary ports and , adding CNOT edge to and causal dependencies , to .
Heuristic selected: SA Sequence Distance (Simulated annealing minimizing cat-state sequence span). Click Next >, Play, or click any dashed edge in Panel 1 to step through Algorithm 1.
Target Bipartite ZX-State
Spiders copy the horizontal topological positions from the Global Digraph, updating with each added edge. All ports exit to the right boundary as output qubits q_0..q_6 (quantum state preparation). Bold edges form spanning forest F from roots r_k (blue boxes).
Topological Grid Alignment & Post-Extraction Qubit Reuse
Because D_global is guaranteed acyclic and every port satisfies Lemma III.7 or Lemma III.8, CatStateExtractor extracts a CNOT circuit in linear time, followed by interval-coloring qubit reuse.
Step through to see how is aligned onto qubit wires and translated into CNOT gates.
Select Qubit Reuse Strategy (Switch Dynamically Above Circuit)
Compiled Quantum Circuit Diagram (9 Physical Qubits, 15 CNOTs, Depth 8)
Data wires q_0..q_6 persist to the output boundary; flag wires q_7..q_8 are measured and recycled when Qubit Reuse is enabled.
RX 2
R 3
R 5
R 6
R 0
CX 2 0
CX 0 3
CX 2 5
CX 0 6
CX 2 0
M 0
RX 0
R 7
CX 0 7
CX 7 5
RX 1
R 8
CX 1 8
CX 1 6
R 4
CX 8 4
CX 8 3
CX 0 4
CX 7 3
CX 0 7
CX 1 8
M 8
M 7
DETECTOR rec[-2]
DETECTOR rec[-3]
DETECTOR rec[-1][[7, 1, 3]] Steane Code — Simulation Results
Circuit-level depolarizing noise (p = 0.001, 1.0e+8 Stim shots per heuristic) comparing SpiderCSS against Flag at Origin (FaO) with 95% Wilson confidence intervals.
Evaluated Heuristics vs. Flag at Origin for [[7, 1, 3]]
| Method / Heuristic | CNOTs | Flags | Sim. Qubits Opt (Q / D) | Depth Opt (Q / D) | Logical Error Rate (95% CI) | Acceptance Rate (95% CI) | Action |
|---|---|---|---|---|---|---|---|
Flag at Origin (FaO) | 15 | 3 | 8 / 15 | 10 / 8 | [2.1, 2.2] × 10^-5 | [0.9870, 0.9871] | |
SpiderCSS (Earliest Start)Best LER | 15 | 3 | 8 / 12 | 10 / 5 | [2.3, 2.5] × 10^-5 | [0.9870, 0.9871] | |
SpiderCSS (Seq. Dist. / Joint) | 15 | 3 | 8 / 12 | 10 / 5 | [2.3, 2.5] × 10^-5 | [0.9870, 0.9871] | |
SpiderCSS (Crit. Path) | 15 | 3 | 8 / 12 | 10 / 5 | [2.4, 2.6] × 10^-5 | [0.9870, 0.9871] | |
SpiderCSS (Active Spider) | 15 | 3 | 8 / 12 | 10 / 5 | [2.4, 2.6] × 10^-5 | [0.9870, 0.9871] | |
SpiderCSS (Seq. Dist. SA)Active in Phase 3 | 15 | 3 | 8 / 12 | 10 / 5 | [2.5, 2.7] × 10^-5 | [0.9870, 0.9871] |
SpiderCSS vs. Flag at Origin Across 18 Benchmarked CSS Codes
Interactive reproduction of Figure 1, Figure 8, and Table I from the paper across 95 Stim Monte Carlo simulation runs (distances d = 3 to 15, up to n = 144 physical qubits).
Logical Error Rate vs. Acceptance Rate Improvement (%)
Circuit Depth vs. Simultaneous Qubits Improvement (%)
Table I: Resource Overhead, Logical Error Rate & Acceptance Rate Comparison
Bold entries indicate the best result for each CSS state. Click any column header to sort, or click Load in Studio ↑ to inspect that code in Phases 1–5.
* Note: Logical error rates marked — were not estimated as the code-capacity syndrome lookup table exceeded memory. For the 4 largest codes (d ≥ 12), values marked with * indicate simulations performed at physical error rate p = 0.0001 instead of p = 0.001.